1. Field of the Invention
This invention relates to integrated circuits and the fabrication of such circuits and, more specifically, to a method of integrating an n-channel vertical double diffused MOS (VDMOS) structure into an N-well CMOS-based bipolar CMOS (BiCMOS) process flow and the device.
2. Brief Description of the Prior Art
For many years, attempts have been made to combine several functions on the same semiconductor chip in order to reduce the number of chips required in a system, improve the overall reliability of the system and reduce the size of the system. Many applications, for example, require a combination of high power, digital logic and analog functions.
A typical device used for power functions has been the vertical DMOS (VDMOS) transistor which is an asymmetric, short-channel, NMOS transistor capable of withstanding high drain-source voltages in the OFF state, but which has very low series resistance in the ON state. While some types of devices can meet these requirements, they either consume excessive power or occupy a large amount of silicon real estate, thereby preventing cost-effective integration. In the past, BiCMOS processes capable of integrating the VDMOS device have been based upon standard bipolar process flows while using a P-well CMOS approach to support the logic functions. However, these bipolar-oriented approaches generally lead to low device packing densities due to the deep P+ isolation diffusions required. Furthermore, the P-well CMOS fabrication procedures are often incompatible with most present standard cell fabrication procedures which are based upon N-well CMOS processes.
At present, BiCMOS processes accommodating VDMOS devices have been based upon conventional bipolar technology. Here, an N+ buried layer is selectively diffused into a p-type substrate, followed by an n-type epitaxial deposition. After standard isolation techniques, the basic bipolar CMOS and VDMOS devices are built as discussed in the U.S. Patent of Curran (4,325,180). In such a process, a P-well is provided to house the NMOS transistors while the PMOS devices are built in the epitaxial layer.
In order to build the VDMOS structure, a common diffusion mask edge is typically used to self-align both the p-type DMOS well (D-well) and the N+ source regions. Since the D-well is diffused into the n-type epitaxial layer and the N+ source is diffused into the D-well, a short lateral p-type region (i.e., the channel) is formed along the silicon surface between the two n-type regions. Most present BiCMOS processes use polysilicon as the common diffusion edge, resulting in a self-aligned device structure. Typically, the same polysilicon layer is used to form both the CMOS and VDMOS gates.
Several problems arise with the present bipolar-oriented BiCMOS processes as follows:
1) The majority of present advanced BiCMOS processes are driven from an N-well CMOS starting point. In this approach, p-type epitaxial silicon rather than n-type is used. As a result, the VDMOS device as originally conceived will no longer function.
2) The VDMOS channel length is determined by the difference in the DMOS well and source lateral diffusions. Thus, efforts to reduce the D-well junction depth in order to improve the performance of the VDMOS structure in the ON state through reduced VDMOS cell JFET resistance can lead to extremely short channel lengths which cannot withstand the high reverse voltage in the OFF state. This problem is exacerbated by the fact that the lateral diffusion is less than the vertical diffusion and that oxidation-induced phosphorus pile-up at the n-epi (epitaxially deposited) surface can further reduce the D-well lateral diffusion.
3) Since the polysilicon used for the VDMOS gate electrode is the same as that used for the CMOS gates, the heat-cycling associated with the deep D-well diffusion will impact both the channel stop and threshold voltage (Vt) implants, leading to increased MOS scaling problems, such as Vt rolloff, punchthrough and channel width reduction.
4) Present VDMOS device designs use a lateral DMOS (LDMOS) structure to terminate the structure at the edges. This technique uses a tapered field oxide to support the high voltage by spreading the electric field in the oxide as the gate polysilicon steps up onto the field oxide. This need for a sloped moat/field oxide transition is opposed to the direction of current LOCOS techniques which attempt to minimize the field oxide "bird's beak".
5) There is a direct coupling of the DMOS voltage capability and the NPN Ft (transition frequency, a FIGURE of merit for speed of the NPN transistor) performance when the NPN base and emitter regions are used as the DMOS backgate and source regions, respectively, as is often done in BiCMOS/VDMOS processes. While a thin vertical base width improves the NPN Ft, it results in a short lateral channel length, which can compromise DMOS BVdss. Recently, shallow arsenic emitters have been used to achieve adequate DMOS BVdss (breakdown voltage from drain to source with back gate short circuited). This, however, leads to slower NPN transistors in the merged BiCMOS process since the base depth cannot be scaled too much or low avalanche DMOS BVdss will occur due to junction curvature effects.
The above noted problems have been minimized to some extent by use of a fabrication process set forth in application U.S. Ser. No. 07/120,558 of Hutter et al., filed Nov. 13, 1987, for High Voltage Merged Bipolar/MOS Technology, which is assigned to the assignee of the subject application, now U.S. Pat. No. 4,994,887 wherein CMOS and bipolar transistor have been formed on a single chip using a p-type epitaxial layer, the contents of this application being incorporated herein in its entirety by reference. In that application, the integrated circuit uses a P+ substrate upon which a P- epitaxial layer is formed. N+ regions are formed in the first P- epitaxial layer. The N+ regions provide low resistance regions for the PMOS transistors and the NPN transistors, while the P+ substrate provides a low resistance region for the NMOS transistors. Alternatively, a P+ region can be formed in the first P- epitaxial layer under the NMOS device, but isolated from the N+ regions. This provides low resistance areas for each of the respective devices while accommodating high voltage NPN transistors.
In another aspect of the above noted application, the high temperature bipolar diffusion and oxidation cycles are performed before the CMOS active region definition in order to maintain the characteristics of the NMOS and PMOS devices. This provides the technical advantage of allowing standard CMOS cells to be used in the design of the digital/analog circuits.
In yet another aspect of the above noted application, a nitride layer is formed over the surface of the integrated circuit prior to the diffusion of the base regions in order to act as an oxidation barrier. This provides an inert anneal which minimizes damage due to silicon oxidation during the diffusion. Alternatively, the nitride layer can be formed prior to implantation in order to reduce damage to the silicon during the ion implantation process. It may also be desirable to leave the nitride layer over the base region during other high temperature cycles, such as thermal oxidation. However, the problem of providing DMOS transistors on the same chip in conjunction with the CMOS and bipolar transistors was not solved therein.